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APPLY FOR THE POSITION
Job Type:
Full-Time
Location:
Chicago, IL USA
Junior FPGA Engineer

‍

About Spartak Trading LLC

Spartak Trading is a proprietary trading firm that is technology-driven, deploying our capital across a broad range of asset classes, instruments, and strategies in financial markets. Spartak Trading is based in Chicago and is a member firm of CME Group and Eurex Exchange.

Spartak Trading LLC is a privately held, proprietary trading firm in Chicago, and we have memberships at the CME Group and Eurex exchanges. Spartak maintains a low profile and doesn't advertise or solicit customers. Over the past few years, we have developed our proprietary trading systems for internal use at various exchanges and we are looking to expand our development team through internship programs and recruitment at various universities.


The Role

We are seeking a Junior FPGA Engineer with experience in SystemVerilog and Linux-based development flows to contribute to our hardware engineering effort. As a Junior FPGA Engineer, you will be responsible for designing, simulating, and verifying RTL for real production hardware in a high-discipline, quality-first engineering environment. Prior experience in the financial industry is preferred but not required; we'll teach you the domain.

Responsibilities

  • Collaborate with the team to understand design requirements and translate them into RTL implementations.
  • Design and develop synchronous/asynchronous digital logic in SystemVerilog.
  • Develop and maintain simulation testbenches to verify functional correctness of RTL modules.
  • Debug functional and timing issues using waveform analysis, simulator logs, and tool reports.
  • Run synthesis and implementation flows for FPGA targets and assist in achieving timing closure.
  • Integrate RTL blocks with on-chip interconnects and external interfaces.
  • Participate in code review, regression testing, and design documentation.
  • Provide technical support and contribute to continuous improvement of build and verification infrastructure.

Qualifications

Must have

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience in RTL design; 5+ years of experience in lieu of a degree.
  • Working knowledge of SystemVerilog or Verilog, including modules, interfaces, packages, parameterization, and basic assertions.
  • Solid grasp of synchronous digital design fundamentals: clocking, pipelining, FIFOs, handshaking, and clock-domain crossing.
  • Experience with at least one commercial HDL simulator and waveform debug.
  • Strong command of Linux: bash, Make, and editing build scripts.
  • Familiarity with version control systems (e.g., Git, SVN, ClearCase).
  • Some scripting ability in TCL, Python, or a comparable language.

Nice to have

  • Experience with cocotb, UVM, or constrained-random verification.
  • Exposure to Xilinx/AMD Vivado or Intel Quartus implementation flows.
  • Familiarity with on-chip interconnects (Avalon, AXI, AXI-Stream) or off-chip interfaces (Ethernet, PCIe).
  • Experience with high clock speed designs.
  • Basic understanding of timing closure: setup/hold, false paths, multicycle paths.
  • Any experience with C/C++, kernel modules, or host-side driver code.
  • Open-source contributions or a portfolio with HDL work.
APPLY FOR THE POSITION

Apply Today

Please fill out the application—if there’s a fit, we’ll be in touch.

Junior FPGA Engineer

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